diff options
| author | James Clark <james.clark@linaro.org> | 2025-06-09 11:19:05 +0100 |
|---|---|---|
| committer | Suzuki K Poulose <suzuki.poulose@arm.com> | 2025-09-02 09:12:57 +0100 |
| commit | 52c0164b2526bce7013fca193e076f6d9eec9c95 (patch) | |
| tree | 8676975f8c31fb72c0372b038edc05d748616695 /drivers/hwtracing | |
| parent | 1b237f190eb3d36f52dffe07a40b5eb210280e00 (diff) | |
coresight: trbe: Add ISB after TRBLIMITR write
DEN0154 states that hardware will be allowed to ignore writes to TRB*
registers while the trace buffer is enabled. Add an ISB to ensure that
it's disabled before clearing the other registers.
This is purely defensive because it's expected that arm_trbe_disable()
would be called before teardown which has the required ISB.
Fixes: a2b579c41fe9 ("coresight: trbe: Remove redundant disable call")
Signed-off-by: James Clark <james.clark@linaro.org>
Reviewed-by: Yeoreum Yun <yeoreum.yun@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20250609-james-cs-trblimitr-isb-v1-1-3a2aa4ee6770@linaro.org
Diffstat (limited to 'drivers/hwtracing')
| -rw-r--r-- | drivers/hwtracing/coresight/coresight-trbe.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index 8267dd1a2130..10f3fb401edf 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -257,6 +257,7 @@ static void trbe_drain_and_disable_local(struct trbe_cpudata *cpudata) static void trbe_reset_local(struct trbe_cpudata *cpudata) { write_sysreg_s(0, SYS_TRBLIMITR_EL1); + isb(); trbe_drain_buffer(); write_sysreg_s(0, SYS_TRBPTR_EL1); write_sysreg_s(0, SYS_TRBBASER_EL1); |