diff options
| author | Mark Brown <broonie@kernel.org> | 2025-01-10 15:01:33 +0000 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2025-01-10 15:01:33 +0000 |
| commit | 89b37e49929653b7c350aac7fb2b96a052533015 (patch) | |
| tree | 9556c9c4f693b4cb69da77f1e717abeea36f0a23 /drivers/spi/spi-cadence-quadspi.c | |
| parent | 5e56618e1593a9eb9d72dc9433ac7a02a6c48c8f (diff) | |
| parent | f0006897a96c736623ddeb9b68c3880eb5cdebe7 (diff) | |
spi-nand/spi-mem DTR support
Merge series from Miquel Raynal <miquel.raynal@bootlin.com>:
Here is a (big) series supposed to bring DTR support in SPI-NAND.
Diffstat (limited to 'drivers/spi/spi-cadence-quadspi.c')
| -rw-r--r-- | drivers/spi/spi-cadence-quadspi.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 594408d53400..0cd37a7436d5 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1433,7 +1433,7 @@ static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op) struct cqspi_flash_pdata *f_pdata; f_pdata = &cqspi->f_pdata[spi_get_chipselect(mem->spi, 0)]; - cqspi_configure(f_pdata, mem->spi->max_speed_hz); + cqspi_configure(f_pdata, op->max_freq); if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { /* @@ -1682,6 +1682,7 @@ static const struct spi_controller_mem_ops cqspi_mem_ops = { static const struct spi_controller_mem_caps cqspi_mem_caps = { .dtr = true, + .per_op_freq = true, }; static int cqspi_setup_flash(struct cqspi_st *cqspi) |