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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2025-10-01 17:41:15 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2025-10-01 17:41:15 -0700 |
| commit | 42cbaeec987b9fb91045060f2e7ce3152458ead9 (patch) | |
| tree | e69718fcf56bf0f6e51fc62936f00da5beb12a97 /include/soc | |
| parent | 38057e323657695ec8f814aff0cdd1c7e00d3e9b (diff) | |
| parent | 65d2419f931c08ead6722fbb9d4bd8cecb25a7e3 (diff) | |
Merge tag 'soc-arm-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC updates from Arnd Bergmann:
"The at91 power management code and the TI AM33 platform each get a few
updates for robustness, the other changes are just minor cleanups"
* tag 'soc-arm-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
ARM: versatile: clock: convert from round_rate() to determine_rate()
ARM: rockchip: remove REGULATOR conditional to PM
ARM: at91: pm: Remove 2.5V regulator
ARM: OMAP2+: clock: convert from round_rate() to determine_rate()
ARM: OMAP1: clock: convert from round_rate() to determine_rate()
ARM: mach-hpe: Rework support and directory structure
arm: omap2: use string choices helper
ARM: OMAP2+: pm33xx-core: ix device node reference leaks in amx3_idle_init
ARM: OMAP2+: use IS_ERR_OR_NULL() helper
ARM: AM33xx: Implement TI advisory 1.0.36 (EMU0/EMU1 pins state on reset)
ARM: at91: pm: save and restore ACR during PLL disable/enable
ARM: at91: pm: fix MCKx restore routine
ARM: at91: pm: fix .uhp_udp_mask specification for current SoCs
ARM: shmobile: rcar-gen2: Use SZ_256K definition
Diffstat (limited to 'include/soc')
| -rw-r--r-- | include/soc/at91/sama7-sfrbu.h | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/include/soc/at91/sama7-sfrbu.h b/include/soc/at91/sama7-sfrbu.h index 76b740810d34..8cee48d1ae2c 100644 --- a/include/soc/at91/sama7-sfrbu.h +++ b/include/soc/at91/sama7-sfrbu.h @@ -18,13 +18,6 @@ #define AT91_SFRBU_PSWBU_SOFTSWITCH (1 << 1) /* Power switch BU source selection */ #define AT91_SFRBU_PSWBU_CTRL (1 << 0) /* Power switch BU control */ -#define AT91_SFRBU_25LDOCR (0x0C) /* SFRBU 2.5V LDO Control Register */ -#define AT91_SFRBU_25LDOCR_LDOANAKEY (0x3B6E18 << 8) /* Specific value mandatory to allow writing of other register bits. */ -#define AT91_SFRBU_25LDOCR_STATE (1 << 3) /* LDOANA Switch On/Off Control */ -#define AT91_SFRBU_25LDOCR_LP (1 << 2) /* LDOANA Low-Power Mode Control */ -#define AT91_SFRBU_PD_VALUE_MSK (0x3) -#define AT91_SFRBU_25LDOCR_PD_VALUE(v) ((v) & AT91_SFRBU_PD_VALUE_MSK) /* LDOANA Pull-down value */ - #define AT91_FRBU_DDRPWR (0x10) /* SFRBU DDR Power Control Register */ #define AT91_FRBU_DDRPWR_STATE (1 << 0) /* DDR Power Mode State */ |