diff options
| author | Alex Elder <elder@riscstar.com> | 2025-07-02 06:37:07 -0500 |
|---|---|---|
| committer | Yixun Lan <dlan@gentoo.org> | 2025-07-07 21:54:16 +0800 |
| commit | c479d7cf06c3d65532442fa368b058e05dbba1a2 (patch) | |
| tree | ea770116c0addb028b192506fed13e043de947bd /include/soc | |
| parent | 024b84f661674dcfa1341c90ce654c485c4ab756 (diff) | |
reset: spacemit: add support for SpacemiT CCU resets
Implement reset support for SpacemiT CCUs. A SpacemiT reset controller
device is an auxiliary device associated with a clock controller (CCU).
This patch defines the reset controllers for the MPMU, APBC, and MPMU
CCUs, which already define clock controllers. It also adds RCPU, RCPU2,
and ACPB2 CCUs, which only define resets.
Signed-off-by: Alex Elder <elder@riscstar.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20250702113709.291748-6-elder@riscstar.com
Signed-off-by: Yixun Lan <dlan@gentoo.org>
Diffstat (limited to 'include/soc')
| -rw-r--r-- | include/soc/spacemit/k1-syscon.h | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/include/soc/spacemit/k1-syscon.h b/include/soc/spacemit/k1-syscon.h index 53eff7691f33..c59bd7a38e5b 100644 --- a/include/soc/spacemit/k1-syscon.h +++ b/include/soc/spacemit/k1-syscon.h @@ -127,4 +127,34 @@ to_spacemit_ccu_adev(struct auxiliary_device *adev) #define APMU_EMAC0_CLK_RES_CTRL 0x3e4 #define APMU_EMAC1_CLK_RES_CTRL 0x3ec +/* RCPU register offsets */ +#define RCPU_SSP0_CLK_RST 0x0028 +#define RCPU_I2C0_CLK_RST 0x0030 +#define RCPU_UART1_CLK_RST 0x003c +#define RCPU_CAN_CLK_RST 0x0048 +#define RCPU_IR_CLK_RST 0x004c +#define RCPU_UART0_CLK_RST 0x00d8 +#define AUDIO_HDMI_CLK_CTRL 0x2044 + +/* RCPU2 register offsets */ +#define RCPU2_PWM0_CLK_RST 0x0000 +#define RCPU2_PWM1_CLK_RST 0x0004 +#define RCPU2_PWM2_CLK_RST 0x0008 +#define RCPU2_PWM3_CLK_RST 0x000c +#define RCPU2_PWM4_CLK_RST 0x0010 +#define RCPU2_PWM5_CLK_RST 0x0014 +#define RCPU2_PWM6_CLK_RST 0x0018 +#define RCPU2_PWM7_CLK_RST 0x001c +#define RCPU2_PWM8_CLK_RST 0x0020 +#define RCPU2_PWM9_CLK_RST 0x0024 + +/* APBC2 register offsets */ +#define APBC2_UART1_CLK_RST 0x0000 +#define APBC2_SSP2_CLK_RST 0x0004 +#define APBC2_TWSI3_CLK_RST 0x0008 +#define APBC2_RTC_CLK_RST 0x000c +#define APBC2_TIMERS0_CLK_RST 0x0010 +#define APBC2_KPC_CLK_RST 0x0014 +#define APBC2_GPIO_CLK_RST 0x001c + #endif /* __SOC_K1_SYSCON_H__ */ |