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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Generic MMIO GPIO
maintainers:
- Linus Walleij <linusw@kernel.org>
- Bartosz Golaszewski <brgl@bgdev.pl>
description:
Some simple GPIO controllers may consist of a single data register or a pair
of set/clear-bit registers. Such controllers are common for glue logic in
FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped
NAND-style parallel busses.
properties:
compatible:
enum:
- brcm,bcm6345-gpio
- ni,169445-nand-gpio
- wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller
- intel,ixp4xx-expansion-bus-mmio-gpio
big-endian: true
'#gpio-cells':
const: 2
gpio-controller: true
little-endian: true
reg:
minItems: 1
description:
A list of registers in the controller. The width of each register is
determined by its size. All registers must have the same width. The number
of GPIOs is set by the width, with bit 0 corresponding to GPIO 0, unless
the ngpios property further restricts the number of used lines.
items:
- description:
Register to READ the value of the GPIO lines. If GPIO line is high,
the bit will be set. If the GPIO line is low, the bit will be cleared.
This register may also be used to drive GPIOs if the SET register is
omitted.
- description:
Register to SET the value of the GPIO lines. Setting a bit in this
register will drive the GPIO line high.
- description:
Register to CLEAR the value of the GPIO lines. Setting a bit in this
register will drive the GPIO line low. If this register is omitted,
the SET register will be used to clear the GPIO lines as well, by
actively writing the line with 0.
- description:
Register to set the line as OUTPUT. Setting a bit in this register
will turn that line into an output line. Conversely, clearing a bit
will turn that line into an input.
- description:
Register to set this line as INPUT. Setting a bit in this register
will turn that line into an input line. Conversely, clearing a bit
will turn that line into an output.
reg-names:
minItems: 1
maxItems: 5
items:
enum:
- dat
- set
- clr
- dirout
- dirin
native-endian: true
ngpios:
minimum: 1
maximum: 63
description:
If this property is present the number of usable GPIO lines are restricted
to the first 0 .. ngpios lines. This is useful when the GPIO MMIO register
has 32 bits for GPIO but only the first 12 are actually connected to
real electronics, and then we set ngpios to 12.
no-output:
$ref: /schemas/types.yaml#/definitions/flag
description:
If this property is present, the controller cannot drive the GPIO lines.
if:
properties:
compatible:
contains:
const: intel,ixp4xx-expansion-bus-mmio-gpio
then:
$ref: /schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml#
patternProperties:
"^.+-hog(-[0-9]+)?$":
type: object
required:
- gpio-hog
required:
- compatible
- reg
- reg-names
- '#gpio-cells'
- gpio-controller
unevaluatedProperties: false
examples:
- |
gpio@1f300010 {
compatible = "ni,169445-nand-gpio";
reg = <0x1f300010 0x4>;
reg-names = "dat";
gpio-controller;
#gpio-cells = <2>;
};
gpio@e0100000 {
compatible = "wd,mbl-gpio";
reg-names = "dat";
reg = <0xe0100000 0x1>;
#gpio-cells = <2>;
gpio-controller;
no-output;
};
gpio@fffe0406 {
compatible = "brcm,bcm6345-gpio";
reg-names = "dirout", "dat";
reg = <0xfffe0406 2>, <0xfffe040a 2>;
ngpios = <15>;
native-endian;
gpio-controller;
#gpio-cells = <2>;
};
bus@c4000000 {
compatible = "intel,ixp42x-expansion-bus-controller", "syscon";
reg = <0xc4000000 0x30>;
native-endian;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0x0 0x50000000 0x01000000>;
dma-ranges = <0 0x0 0x50000000 0x01000000>;
gpio@1,0 {
compatible = "intel,ixp4xx-expansion-bus-mmio-gpio";
gpio-controller;
#gpio-cells = <2>;
big-endian;
reg = <1 0x00000000 0x2>;
reg-names = "dat";
intel,ixp4xx-eb-write-enable = <1>;
};
};
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